Template:X86 protected mode interrupts

x86 Interrupt descriptor table items^[1] [edit table]
Int. №		Mnem.	Type	Err. code^[a]	Name	Source
hex	dec	Mnem.	Type	Err. code^[a]	Name	Source
0x00	0	#DE	Fault	No	Divide Error	DIV and IDIV instructions.
0x01	1	#DB	Trap	No	Debug Exception	Instruction, data, and I/O breakpoints; single-step; and others.
0x02	2	NMI^[b]	Interrupt	No	NMI Interrupt	Nonmaskable external interrupt.
0x03	3	#BP	Trap	No	Breakpoint	INT3 instruction.
0x04	4	#OF	Trap	No	Overflow	INTO instruction.
0x05	5	#BR	Fault	No	BOUND Range Exceeded	BOUND instruction.
0x06	6	#UD	Fault	No	Invalid Opcode (Undefined Opcode)	UD instruction or reserved opcode.
0x07	7	#NM	Fault	No	Device Not Available (No Math Coprocessor)	Floating-point or WAIT/FWAIT instruction.
0x08	8	#DF	Abort	Yes (zero)	Double Fault	Any instruction that can generate an exception, an NMI, or an INTR.
0x09	9	—	Fault	No	Coprocessor Segment Overrun (reserved)	Floating-point instruction.
0x0A	10	#TS	Fault	Yes	Invalid TSS	Task switch or TSS access.
0x0B	11	#NP	Fault	Yes	Segment Not Present	Loading segment registers or accessing system segments.
0x0C	12	#SS	Fault	Yes	Stack-Segment Fault	Stack operations and SS register loads.
0x0D	13	#GP	Fault	Yes	General Protection	Any memory reference and other protection checks.
0x0E	14	#PF	Fault	Yes	Page Fault	Any memory reference.
0x0F	15	—		No	Intel reserved. Do not use.
0x10	16	#MF	Fault	No	x87 FPU Floating-Point Error (Math Fault)	x87 FPU floating-point or WAIT/FWAIT instruction.
0x11	17	#AC	Fault	Yes (zero)	Alignment Check	Any data reference in memory.
0x12	18	#MC	Abort	No	Machine Check	Error codes (if any) and source are model dependent.
0x13	19	#XM	Fault	No	SIMD Floating-Point Exception	SSE/SSE2/SSE3 floating-point instructions
0x14	20	#VE	Fault	No	Virtualization Exception	EPT violations
0x15	21	#CP	Fault	Yes	Control Protection Exception	RET, IRET, RSTORSSP, and SETSSBSY instructions can generate this exception. When CET indirect branch tracking is enabled, this exception can be generated due to a missing ENDBRANCH instruction at target of an indirect call or jump.
0x16 ⋮ 0x1f	22 ⋮ 31	Unknown			Reserved for future use as CPU exception vectors.
0x20 ⋮ 0xff	32 ⋮ 255	—	Interrupt	No	—	External interrupts.

^ This column determines whether the interrupt pushes an exception code to the interrupt handler stack, or not. For some exceptions, this pushes only a zero number
^ The official Intel documentation does not assign an official mnemonic to this interrupt, but abbreviation “NMI” is widely used to refer to this interrupt, even in the Intel docs itself.

^ Intel Corporation (April 2022). Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B, 3C & 3D): System Programming Guide. Intel Corporation. pp. 6-1 to 6-58.

[x86_idt_errcode-2] This column determines whether the interrupt pushes an exception code to the interrupt handler stack, or not. For some exceptions, this pushes only a zero number

[x86_idt_nmi-3] The official Intel documentation does not assign an official mnemonic to this interrupt, but abbreviation “NMI” is widely used to refer to this interrupt, even in the Intel docs itself.

[1] Intel Corporation (April 2022). Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B, 3C & 3D): System Programming Guide. Intel Corporation. pp. 6-1 to 6-58.

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[a]

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Template:X86 protected mode interrupts

Usage note

Interrupt table